The invention relates to electronic devices, and, more particularly, to ferroelectric memories and methods.
In current semiconductor DRAM memory, the typical memory cell consists of a capacitor for electrical charge storage and an access transistor for connecting the storage capacitor with a bitline and sense amplifier for reads and writes. DRAM memory has the drawback of being volatile, but the nonvolatile alternative flash EEPROM memory suffers from slow writes. Ferroelectric memory as been proposed in which a capacitor with ferroelectric material between the capacitor plates stores an electric polarization and is nonvolatile. Basically, a ferroelectric memory cell can be read by first turning on the access transistor (essentially not affecting the bitline potential) and then pulsing the other ferroelectric capacitor plate with a voltage which causes the bitline potential to rise to one of two levels, depending upon whether or not the pulse reversed the polarization of the ferroelectric material. A DRAM-type sense amplifier can then latch the bitline potential provided a reference voltage is supplied which lies between the two levels. The reference voltage could be generated by a dummy ferroelectric capacitor cell.
Tanabe et al, A High Density 1T/2C Cell with Vcc/2 Reference Level for High Stable FeRAMs, 1997 IEEE IEDM Tech. Dig. 34.5.1 discloses a variation of the known ferroelectric memory cell array with two ferroelectric capacitors polarized in opposite directions in each cell.